单片机源程序如下:
- module fsk_freq_ctrl(clk,data_in,freq_ctrl,rst);
- input clk;
- input [7:0] data_in;
- input rst;
- output [11:0] freq_ctrl;
- //reg [4:0] q;
- //parameter i;
- reg [4:0] i;
- wire [4:0] q;
- reg [11:0] freq_ctrl;
- reg [7:0] a;
- always @(posedge clk or negedge rst)
- if(rst==1'b0)
- begin
- a <= data_in;
- freq_ctrl <=12'b000000000000;
- end
- else if(a[i]!=0)
- begin
- freq_ctrl <= 12'd20;
- end
- else if(a[i]==0)
- freq_ctrl <= 12'd10;
-
- always @(posedge clk or negedge rst)
- if(!rst)
- i=5'b0;
- else if(i==5'd7)
- begin
- i <= 5'b0; end
- else i <= i+1;
- endmodule
- //for(i=0;i<8;i=i+1)
- // if(data_in[i]==0)
- // freq_ctrl=12'd10;
- // else
- // freq_ctrl=12'd20;
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