LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.STD_LOGIC_ARItH.all;
ENTITY VHDL1 IS
PORT (CLK,RST,EN : IN STD_LOGIC;
Disp_Decode1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUT1:OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END VHDL1;
ARCHITECTURE BEHAV OF VHDL1 IS
SIGNAL tmb,Disp_Temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tma : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal clk1hz:STD_LOGIC;
SIGNAL count : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal Clk_Count1:STD_LOGIC_VECTOR(13 DOWNTO 0);
signal Disp_Decode: STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
process(Clk)
begin
if(Clk'event and Clk='1') then
if(Clk_Count1<10000) then
Clk_Count1<=Clk_Count1+1;
else
Clk_Count1<="00000000000001";
end if;
end if;
end process;
Clk1Hz<=Clk_Count1(13);
PROCESS(CLK1hz,EN)
BEGIN
IF RST='0' THEN tmb <=(OTHERS=>'0');tma <=(OTHERS=>'0');
ELSIF CLK1hz'EVENT AND CLK1hz='1' THEN
IF EN='1' THEN
if tmb="1001" then tmb<="0000";
if tma="101" then tma<="000";
else tma<=tma+1;
END IF;
else tmb<=tmb+1;
END IF;
END IF;
END IF;
--dout<=conv_std_logic_vector(conv_integer(tmb)+conv_integer(tma)*10,6);
--dout<=tmb;
-- dout1<=tma;
END PROCESS;
process(clk)
begin
IF CLK'EVENT AND CLK='1' THEN
count<=count+1;
Disp_Decode1<=Disp_Decode;
end if;
END PROCESS;
process(count)
begin
case count is
WHEN "00"|"10"=>dout1<="10";Disp_Temp<=tmb;
WHEN "01"|"11"=> dout1<="01";Disp_Temp<='0'& tma;
WHEN OTHERS =>NULL;
END CASE;
END PROCESS;
process(Disp_Temp) --显示转换
begin
case Disp_Temp is
when "0000"=>Disp_Decode<="0111111"; --0
when "0001"=>Disp_Decode<="0000110"; --1
when "0010"=>Disp_Decode<="1011011"; --2
when "0011"=>Disp_Decode<="1001111"; --3
when "0100"=>Disp_Decode<="1100110"; --4
when "0101"=>Disp_Decode<="1101101"; --5
when "0110"=>Disp_Decode<="1111101"; --6
when "0111"=>Disp_Decode<="0000111"; --7
when "1000"=>Disp_Decode<="1111111"; --8
when "1001"=>Disp_Decode<="1101111"; --9
-- when 10=>Disp_Decode<="1000000"; ---
when others=>Disp_Decode<="0000000"; --全灭
end case;
end process;
END BEHAV;
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