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通讯模块SI4438的配置源码

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ID:301559 发表于 2018-4-3 16:20 | 显示全部楼层 |阅读模式
Si443是Silicon labs公司专门针对中国市场推出的一款无线收发神器。其工作频段是425MHz到525MHz。这款芯片的技术参数如下：

参数名称                      SI4432                      SI4463                            SI4438
频率范围              240~960MHz           142-175,284-250           424-525MHz
420-525 850-1050                    
接收灵敏度             -121dBm                        -126dBm                       -124dBm
发射功率                +20Db                             +21Db                            +20Db
关机电流                      50nA                            30nA                             30nA
待机电流                      800nA                           50nA                              50nA
DATA速率                0.123~256K                 0.123~1M                      0.1~500k
接收电流                  18.5mA                          10.0/14mA                       14mA
发射电流                    85mA                            70-80mA                       70-75mA
TX/ RX FIFO              64byte                           64byte                            64byte

单片机源程序如下:
  1. /*! @file radio_config.h
  2. * @brief This file contains the automatically generated
  3. * configurations.
  4. *
  5. * @n WDS GUI Version: 3.2.11.0
  6. * @n Device: Si4438 Rev.: B1                                 
  7. *
  8. * @b COPYRIGHT
  9. * @n Silicon Laboratories Confidential
  10. * @n Copyright 2017 Silicon Laboratories, Inc.
  11. */

  13. #ifndef RADIO_CONFIG_H_
  14. #define RADIO_CONFIG_H_

  16. // USER DEFINED PARAMETERS
  17. // Define your own parameters here

  19. // INPUT DATA
  20. /*
  21. // Crys_freq(Hz): 30000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0   
  22. // MOD_type: 2    Rsymb(sps): 10000    Fdev(Hz): 20000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 2   
  23. // RF Freq.(MHz): 490    API_TC: 29    fhst: 250000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1   
  24. //
  25. // # RX IF frequency is  -468750 Hz
  26. // # WB filter 3 (BW =  92.61 kHz);  NB-filter 3 (BW = 92.61 kHz)
  27. //
  28. // Modulation index: 4
  29. */


  32. // CONFIGURATION PARAMETERS
  33. #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     30000000L
  34. #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x04
  35. #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x07
  36. #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
  37. #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
  38. #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD                                           {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5}


  41. // CONFIGURATION COMMANDS

  43. /*
  44. // Command:                  RF_POWER_UP
  45. // Description:              Command to power-up the device and select the operational mode and functionality.
  46. */
  47. #define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80

  49. /*
  50. // Command:                  RF_GPIO_PIN_CFG
  51. // Description:              Configures the GPIO pins.
  52. */
  53. #define RF_GPIO_PIN_CFG 0x13, 0x04, 0x10, 0x00, 0x00, 0x14, 0x00, 0x00

  55. /*
  56. // Set properties:           RF_GLOBAL_XO_TUNE_2
  57. // Number of properties:     2
  58. // Group ID:                 0x00
  59. // Start ID:                 0x00
  60. // Default values:           0x40, 0x00,
  61. // Descriptions:
  62. //   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
  63. //   GLOBAL_CLK_CFG - Clock configuration options.
  64. */
  65. #define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00

  67. /*
  68. // Set properties:           RF_GLOBAL_CONFIG_1
  69. // Number of properties:     1
  70. // Group ID:                 0x00
  71. // Start ID:                 0x03
  72. // Default values:           0x20,
  73. // Descriptions:
  74. //   GLOBAL_CONFIG - Global configuration settings.
  75. */
  76. #define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60

  78. /*
  79. // Set properties:           RF_INT_CTL_ENABLE_2
  80. // Number of properties:     2
  81. // Group ID:                 0x01
  82. // Start ID:                 0x00
  83. // Default values:           0x04, 0x00,
  84. // Descriptions:
  85. //   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
  86. //   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
  87. */
  88. #define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x38

  90. /*
  91. // Set properties:           RF_FRR_CTL_A_MODE_4
  92. // Number of properties:     4
  93. // Group ID:                 0x02
  94. // Start ID:                 0x00
  95. // Default values:           0x01, 0x02, 0x09, 0x00,
  96. // Descriptions:
  97. //   FRR_CTL_A_MODE - Fast Response Register A Configuration.
  98. //   FRR_CTL_B_MODE - Fast Response Register B Configuration.
  99. //   FRR_CTL_C_MODE - Fast Response Register C Configuration.
  100. //   FRR_CTL_D_MODE - Fast Response Register D Configuration.
  101. */
  102. #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00

  104. /*
  105. // Set properties:           RF_PREAMBLE_TX_LENGTH_9
  106. // Number of properties:     9
  107. // Group ID:                 0x10
  108. // Start ID:                 0x00
  109. // Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00,
  110. // Descriptions:
  111. //   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
  112. //   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
  113. //   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
  114. //   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
  115. //   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
  116. //   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  117. //   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  118. //   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  119. //   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
  120. */
  121. #define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00

  123. /*
  124. // Set properties:           RF_SYNC_CONFIG_5
  125. // Number of properties:     5
  126. // Group ID:                 0x11
  127. // Start ID:                 0x00
  128. // Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4,
  129. // Descriptions:
  130. //   SYNC_CONFIG - Sync Word configuration bits.
  131. //   SYNC_BITS_31_24 - Sync word.
  132. //   SYNC_BITS_23_16 - Sync word.
  133. //   SYNC_BITS_15_8 - Sync word.
  134. //   SYNC_BITS_7_0 - Sync word.
  135. */
  136. #define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00

  138. /*
  139. // Set properties:           RF_PKT_CRC_CONFIG_7
  140. // Number of properties:     7
  141. // Group ID:                 0x12
  142. // Start ID:                 0x00
  143. // Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00,
  144. // Descriptions:
  145. //   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
  146. //   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
  147. //   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
  148. //   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
  149. //   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
  150. //   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
  151. //   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
  152. */
  153. #define RF_PKT_CRC_CONFIG_7 0x11, 0x12, 0x07, 0x00, 0x84, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x02

  155. /*
  156. // Set properties:           RF_PKT_LEN_12
  157. // Number of properties:     12
  158. // Group ID:                 0x12
  159. // Start ID:                 0x08
  160. // Default values:           0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  161. // Descriptions:
  162. //   PKT_LEN - Configuration bits for reception of a variable length packet.
  163. //   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
  164. //   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
  165. //   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
  166. //   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
  167. //   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
  168. //   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
  169. //   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
  170. //   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
  171. //   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
  172. //   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
  173. //   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
  174. */
  175. #define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x07, 0x04, 0x80, 0x00, 0x00, 0x00

  177. /*
  178. // Set properties:           RF_PKT_FIELD_2_CRC_CONFIG_12
  179. // Number of properties:     12
  180. // Group ID:                 0x12
  181. // Start ID:                 0x14
  182. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  183. // Descriptions:
  184. //   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
  185. //   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
  186. //   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
  187. //   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
  188. //   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
  189. //   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
  190. //   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
  191. //   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
  192. //   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
  193. //   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
  194. //   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
  195. //   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
  196. */
  197. #define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  199. /*
  200. // Set properties:           RF_PKT_FIELD_5_CRC_CONFIG_12
  201. // Number of properties:     12
  202. // Group ID:                 0x12
  203. // Start ID:                 0x20
  204. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  205. // Descriptions:
  206. //   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
  207. //   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
  208. //   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
  209. //   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
  210. //   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
  211. //   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
  212. //   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
  213. //   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
  214. //   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
  215. //   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
  216. //   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
  217. //   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
  218. */
  219. #define RF_PKT_FIELD_5_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  221. /*
  222. // Set properties:           RF_PKT_RX_FIELD_3_CRC_CONFIG_9
  223. // Number of properties:     9
  224. // Group ID:                 0x12
  225. // Start ID:                 0x2C
  226. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  227. // Descriptions:
  228. //   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
  229. //   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
  230. //   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
  231. //   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
  232. //   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
  233. //   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
  234. //   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
  235. //   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
  236. //   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
  237. */
  238. #define RF_PKT_RX_FIELD_3_CRC_CONFIG_9 0x11, 0x12, 0x09, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  240. /*
  241. // Set properties:           RF_MODEM_MOD_TYPE_12
  242. // Number of properties:     12
  243. // Group ID:                 0x20
  244. // Start ID:                 0x00
  245. // Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
  246. // Descriptions:
  247. //   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
  248. //   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
  249. //   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
  250. //   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
  251. //   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
  252. //   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
  253. //   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  254. //   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  255. //   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  256. //   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
  257. //   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
  258. //   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
  259. */
  260. #define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x02, 0x00, 0x07, 0x01, 0x86, 0xA0, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x05

  262. /*
  263. // Set properties:           RF_MODEM_FREQ_DEV_0_1
  264. // Number of properties:     1
  265. // Group ID:                 0x20
  266. // Start ID:                 0x0C
  267. // Default values:           0xD3,
  268. // Descriptions:
  269. //   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
  270. */
  271. #define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x76

  273. /*
  274. // Set properties:           RF_MODEM_TX_RAMP_DELAY_8
  275. // Number of properties:     8
  276. // Group ID:                 0x20
  277. // Start ID:                 0x18
  278. // Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
  279. // Descriptions:
  280. //   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
  281. //   MODEM_MDM_CTRL - MDM control.
  282. //   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
  283. //   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
  284. //   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
  285. //   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
  286. //   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
  287. //   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
  288. */
  289. #define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20

  291. /*
  292. // Set properties:           RF_MODEM_BCR_OSR_1_9
  293. // Number of properties:     9
  294. // Group ID:                 0x20
  295. // Start ID:                 0x22
  296. // Default values:           0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
  297. // Descriptions:
  298. //   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
  299. //   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
  300. //   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
  301. //   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
  302. //   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
  303. //   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
  304. //   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
  305. //   MODEM_BCR_GEAR - RX BCR loop gear control.
  306. //   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
  307. */
  308. #define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0x77, 0x01, 0x5D, 0x86, 0x00, 0xAF, 0x02, 0xC2

  310. /*
  311. // Set properties:           RF_MODEM_AFC_GEAR_7
  312. // Number of properties:     7
  313. // Group ID:                 0x20
  314. // Start ID:                 0x2C
  315. // Default values:           0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
  316. // Descriptions:
  317. //   MODEM_AFC_GEAR - RX AFC loop gear control.
  318. //   MODEM_AFC_WAIT - RX AFC loop wait time control.
  319. //   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
  320. //   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
  321. //   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
  322. //   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
  323. //   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
  324. */
  325. #define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x1D, 0x11, 0xEC, 0x80

  327. /*
  328. // Set properties:           RF_MODEM_AGC_CONTROL_1
  329. // Number of properties:     1
  330. // Group ID:                 0x20
  331. // Start ID:                 0x35
  332. // Default values:           0xE0,
  333. // Descriptions:
  334. //   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
  335. */
  336. #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2

  338. /*
  339. // Set properties:           RF_MODEM_AGC_WINDOW_SIZE_3
  340. // Number of properties:     3
  341. // Group ID:                 0x20
  342. // Start ID:                 0x38
  343. // Default values:           0x11, 0x10, 0x10,
  344. // Descriptions:
  345. //   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
  346. //   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
  347. //   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
  348. */
  349. #define RF_MODEM_AGC_WINDOW_SIZE_3 0x11, 0x20, 0x03, 0x38, 0x11, 0x52, 0x52

  351. /*
  352. // Set properties:           RF_MODEM_OOK_PDTC_1
  353. // Number of properties:     1
  354. // Group ID:                 0x20
  355. // Start ID:                 0x40
  356. // Default values:           0x2B,
  357. // Descriptions:
  358. //   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
  359. */
  360. #define RF_MODEM_OOK_PDTC_1 0x11, 0x20, 0x01, 0x40, 0x2A

  362. /*
  363. // Set properties:           RF_MODEM_OOK_CNT1_9
  364. // Number of properties:     9
  365. // Group ID:                 0x20
  366. // Start ID:                 0x42
  367. // Default values:           0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF,
  368. // Descriptions:
  369. //   MODEM_OOK_CNT1 - OOK control.
  370. //   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
  371. //   MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
  372. //   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
  373. //   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
  374. //   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
  375. //   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
  376. //   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
  377. //   MODEM_RSSI_THRESH - Configures the RSSI threshold.
  378. */
  379. #define RF_MODEM_OOK_CNT1_9 0x11, 0x20, 0x09, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x01, 0x20, 0x01, 0x80, 0xFF

  381. /*
  382. // Set properties:           RF_MODEM_RSSI_CONTROL_1
  383. // Number of properties:     1
  384. // Group ID:                 0x20
  385. // Start ID:                 0x4C
  386. // Default values:           0x01,
  387. // Descriptions:
  388. //   MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s).
  389. */
  390. #define RF_MODEM_RSSI_CONTROL_1 0x11, 0x20, 0x01, 0x4C, 0x00

  392. /*
  393. // Set properties:           RF_MODEM_RSSI_COMP_1
  394. // Number of properties:     1
  395. // Group ID:                 0x20
  396. // Start ID:                 0x4E
  397. // Default values:           0x32,
  398. // Descriptions:
  399. //   MODEM_RSSI_COMP - RSSI compensation value.
  400. */
  401. #define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40

  403. /*
  404. // Set properties:           RF_MODEM_CLKGEN_BAND_1
  405. // Number of properties:     1
  406. // Group ID:                 0x20
  407. // Start ID:                 0x51
  408. // Default values:           0x08,
  409. // Descriptions:
  410. //   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
  411. */
  412. #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A

  414. /*
  415. // Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
  416. // Number of properties:     12
  417. // Group ID:                 0x21
  418. // Start ID:                 0x00
  419. // Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
  420. // Descriptions:
  421. //   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
  422. //   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
  423. //   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
  424. //   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
  425. //   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
  426. //   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
  427. //   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
  428. //   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
  429. //   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
  430. //   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
  431. //   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
  432. //   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
  433. */
  434. #define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11

  436. /*
  437. // Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
  438. // Number of properties:     12
  439. // Group ID:                 0x21
  440. // Start ID:                 0x0C
  441. // Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
  442. // Descriptions:
  443. //   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
  444. //   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
  445. //   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
  446. //   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
  447. //   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
  448. //   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
  449. //   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
  450. //   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
  451. //   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
  452. //   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
  453. //   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
  454. //   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
  455. */
  456. #define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1

  458. /*
  459. // Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
  460. // Number of properties:     12
  461. // Group ID:                 0x21
  462. // Start ID:                 0x18
  463. // Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
  464. // Descriptions:
  465. //   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
  466. //   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
  467. //   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
  468. //   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
  469. //   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
  470. //   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
  471. //   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
  472. //   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
  473. //   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
  474. //   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
  475. //   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
  476. //   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
  477. */
  478. #define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00

  480. /*
  481. // Set properties:           RF_PA_MODE_4
  482. // Number of properties:     4
  483. // Group ID:                 0x22
  484. // Start ID:                 0x00
  485. // Default values:           0x08, 0x7F, 0x00, 0x5D,
  486. // Descriptions:
  487. //   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
  488. //   PA_PWR_LVL - Configuration of PA output power level.
  489. //   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
  490. //   PA_TC - Configuration of PA ramping parameters.
  491. */
  492. #define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D

  494. /*
  495. // Set properties:           RF_SYNTH_PFDCP_CPFF_7
  496. // Number of properties:     7
  497. // Group ID:                 0x23
  498. // Start ID:                 0x00
  499. // Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
  500. // Descriptions:
  501. //   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
  502. //   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
  503. //   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
  504. //   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
  505. //   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
  506. //   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
  507. //   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
  508. */
  509. #define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03

  511. /*
  512. // Set properties:           RF_MATCH_VALUE_1_12
  513. // Number of properties:     12
  514. // Group ID:                 0x30
  515. // Start ID:                 0x00
  516. // Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  517. // Descriptions:
  518. //   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
  519. //   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
  520. //   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
  521. //   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
  522. //   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
  523. //   MATCH_CTRL_2 - Configuration of Match Byte 2.
  524. //   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
  525. //   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
  526. //   MATCH_CTRL_3 - Configuration of Match Byte 3.
  527. //   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
  528. //   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
  529. //   MATCH_CTRL_4 - Configuration of Match Byte 4.
  530. */
  531. #define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

  533. /*
  534. // Set properties:           RF_FREQ_CONTROL_INTE_8
  535. // Number of properties:     8
  536. // Group ID:                 0x40
  537. // Start ID:                 0x00
  538. // Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
  539. // Descriptions:
  540. //   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
  541. //   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
  542. //   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
  543. //   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
  544. //   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
  545. //   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
  546. //   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
  547. //   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
  548. */
  549. #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x40, 0x0A, 0xAA, 0xAA, 0x44, 0x44, 0x20, 0xFE


  552. // AUTOMATICALLY GENERATED CODE!
  553. // DO NOT EDIT/MODIFY BELOW THIS LINE!
  554. // --------------------------------------------

  556. #ifndef FIRMWARE_LOAD_COMPILE
  557. #define RADIO_CONFIGURATION_DATA_ARRAY { \
  558.         0x07, RF_POWER_UP, \
  559.         0x08, RF_GPIO_PIN_CFG, \
  560.         0x06, RF_GLOBAL_XO_TUNE_2, \
  561.         0x05, RF_GLOBAL_CONFIG_1, \
  562.         0x06, RF_INT_CTL_ENABLE_2, \
  563.         0x08, RF_FRR_CTL_A_MODE_4, \
  564.         0x0D, RF_PREAMBLE_TX_LENGTH_9, \
  565.         0x09, RF_SYNC_CONFIG_5, \
  566.         0x0B, RF_PKT_CRC_CONFIG_7, \
  567.         0x10, RF_PKT_LEN_12, \
  568.         0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \
  569.         0x10, RF_PKT_FIELD_5_CRC_CONFIG_12, \
  570.         0x0D, RF_PKT_RX_FIELD_3_CRC_CONFIG_9, \
  571.         0x10, RF_MODEM_MOD_TYPE_12, \
  572.         0x05, RF_MODEM_FREQ_DEV_0_1, \
  573.         0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
  574.         0x0D, RF_MODEM_BCR_OSR_1_9, \
  575.         0x0B, RF_MODEM_AFC_GEAR_7, \
  576.         0x05, RF_MODEM_AGC_CONTROL_1, \
  577.         0x07, RF_MODEM_AGC_WINDOW_SIZE_3, \
  578.         0x05, RF_MODEM_OOK_PDTC_1, \
  579. ……………………

  581. …………限于本文篇幅 余下代码请从51黑下载附件…………
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