主控模块程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY master IS
PORT(LEFT,RIGHT,BRAKE,FOG,BACK:IN STD_LOGIC;-定义端口
LP,RP,LR,F,B,BRAKE_LED:OUT STD_LOGIC);
END;
ARCHITECTURE ART OF master IS
BEGIN
BRAKE_LED<=BRAKE;-将刹车信号BRAKE给输出脉冲BRAKE_LED
F<=FOG; -将雾灯模式FOG给输出脉冲F
B<=BACK; -将倒车模式BACK给输出脉冲B
PROCESS(LEFT,RIGHT)
VARIABLE TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
TEMP:=LEFT&RIGHT;
CASE TEMP IS
WHEN"00"=>LP<='0';RP<='0';LR<='0';
WHEN"01"=>LP<='0';RP<='1';LR<='0';右转弯输出脉冲
WHEN"10"=>LP<='1';RP<='0';LR<='0'左转弯输出脉冲;
WHEN OTHERS =>LP<='0';RP<='0';LR<='1';无效
END CASE;
END PROCESS;
END ARCHITECTURE ART;
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