左侧控制模块程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LC IS
PORT(CLK,LP,LR,BRAKE:IN STD_LOGIC;-定义端口
ZLED1,ZLED2:OUT STD_LOGIC);
END ENTITY LC;
ARCHITECTURE ART OF LC IS
BEGIN
ZLED2<=BRAKE; -将刹车输入脉冲BRAKE给ZLED2
PROCESS(CLK,LP,LR)
BEGIN
IF CLK'EVENT AND CLK='1'THEN -上升沿有效
IF(LR='0')THEN
IF(LP='0')THEN - 左转弯输入脉冲LP为高时，左转弯输出信号为高
ZLED1<='0';
ELSE
ZLED1<='1';
END IF;
ELSE
ZLED1<='0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART
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