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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity 111 is
port(clk50m:in std_logic;
rst :in std_logic;
d:out std_logic_vector(3 downto 0);
s:out std_logic_vector(7 downto 0));
end 111;
architecture ab of 111 is
signal t:std_logic_vector(24 downto 0):="0000000000000000000000000";
signal clk:std_logic:='0';
signal cn:integer range 0 to 9;
begin
process(clk50m)
begin
if rising_edge(clk50m) then
if t="10111110101111100000111111"then
t<="0000000000000000000000000";
clk<= not clk;
else t<=t+1;
end if;
end if;
end process;
process(clk,rst,cn)
begin
if rst='0'then cn<=0;
elsif clk'event and clk='1' then
if cn<9 then cn<=cn+1;
else cn <=0;
end if;
end if;
end process;
process(cn)
begin
case cn is
when 0=>d<="1110";s<="00000011";
when 1=>d<="1110";s<="10011111";
when 2=>d<="1110";s<="00100101";
when 3=>d<="1110";s<="00001101";
when 4=>d<="1110";s<="10011001";
when 5=>d<="1110";s<="01001001";
when 6=>d<="1110";s<="11000001";
when 7=>d<="1110";s<="00011111";
when 8=>d<="1110";s<="00000001";
when 9=>d<="1110";s<="00011001";
when others =>null;
end case;
end process;
end architecture ab; |
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