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1.f_div_1.v module f_div_1(clk,div12); input clk; output div12; reg div12; reg [2:0]cnt; always @(posedge clk) begin if(cnt==3'b101) begin div12<=~div12;cnt<=0;end else begin cnt<=cnt+1;end end endmodule 2.f_div_1tb.v `timescale 1ns/100ps module f_div_1tb(); reg clk; wire div12; initial begin clk=0; #500 $stop; end always #10 clk=~clk; f_div_1 U1(clk,div12); endmodule 3.波形图 波形图，有clk波形，无div12波形。
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