分频计模块
library ieee;
use ieee. std_logic_1164. All;
use ieee. std_logic_arith. all;
use ieee. std_logic_unsigned. All;
entity freq is
port(clk_sys : in std_logic;
clk_new: out std_logic);
end freq;
architecture one of freq is
signal set : std_logic;
signal cnt : std_logic_vector ( 17 downto 0 );
begin
process ( clk_sys)
begin
if set ='1'then
cnt <="011111111111111111";
elsif clk_sys'event and clk_sys = '1'then
Cnt <= cnt-1;
end if;
end process;
set<= cnt( 17);
clk_new <= cnt ( 16);
end one;
控制器模块
tibrary ieee;
use ieee. std_logic_1164. All;
use ieee. std_logic_arith. All;
use ieee. std_logic_unsigned. All;
entity step_motor IS
porti( clk : in std_logic;
Starstop : in std_logic;
ForRev : in std_logic :'0';
speed : in std_logic_vector ( 1 domto 0)
ForLED : out std_logic;
RevLED : out std_logic;
coil : out std)_logic_vector (3 domto 0));
end step_motor;
architecture two OF step_motor IS
signal ind_coil: std_logic_vector(3 downto 0):=" 0001";
signal clk_scan : STD_LOGIC;
signal PHASE, DIRECHON : STD_LOGIC;
signal moto:std_logic_vector(3 downto 0);
signal comp : integer range 0 to 2500;
signal osc:std_logic;
begin
Coil<= moto;
P1 : process(clk, osc)
variable delay : integer range 0 to 50;
begin
if(clk'event and clk ='1') then
if delay> = 50 then
delay:=0;osc<= not osc;
else delay :=delay+ 1;
end if;
end if;
if (Osc'event and osc='1') then
case speed is
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