这个工程包括两个文件Edma_interrupt_example.c和edmaIntDispatcher.c，第一个是初始化的程序，第二个为中断服务子程序。最后再附带一个FPGA的Verilog程序，用与产生mcbsp的接收数据。如果想接收更多的数据，修改BUFFSIZE的大小就好了。希望对你有帮助！
下面是第一个文件内容
#include
#include
#include
#include
#include
#include
#include
#define BUFFSIZE 10
#definePING 0
#definePONG 1
Int16 gBufferXmtPing[BUFFSIZE]; // Transmit PINGbuffer
Int16 gBufferXmtPong[BUFFSIZE]; // Transmit PONGbuffer
Int16 gBufferRcvPing[BUFFSIZE]; // Receive PINGbuffer
Int16 gBufferRcvPong[BUFFSIZE]; // Receive PONGbuffer
volatileUint32 intFlag = 0;
Uint32 passStatus = 1;
void tcc1Fxn(void);
void edmaInit(void);
#define WAIT_FOR_2_CLK do{ \
volatile int delayCnt =2; \
while(delayCnt> 0) --delayCnt; \
}while(0)
//#define NumOfWords 100
void init_McBSP0(void);
CSL_Status hwSetupVerify (CSL_McbspHwSetup *,
CSL_McbspHwSetup *
);
CSL_McbspHandle hMcbsp;
//Uint16 xmt[NumOfWords];
//Uint16 rcv[NumOfWords];
CSL_McbspGlobalSetup mcbspGbl = {
CSL_MCBSP_IOMODE_TXDIS_RXDIS ,
CSL_MCBSP_DLBMODE_OFF, //关闭自环模式
CSL_MCBSP_CLKSTP_DISABLE
};
CSL_McbspDataSetup mcbspRxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_8,
1, //frame length
(CSL_McbspWordLen)0,
0,
//CSL_MCBSP_FRMSYNC_IGNORE, //frame sincignore
CSL_MCBSP_FRMSYNC_DETECT,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_1_BIT,
CSL_MCBSP_RJUSTDXENA_RJUST_RZF ,
CSL_MCBSP_INTMODE_ON_READY,
//CSL_MCBSP_INTMODE_ON_FSYNC,
CSL_MCBSP_32BIT_REVERS_DISABLE
};
CSL_McbspDataSetup mcbspTxData = {
CSL_MCBSP_PHASE_SINGLE,
CSL_MCBSP_WORDLEN_8,
1, //每次发送一个元素
(CSL_McbspWordLen)0,
0,
CSL_MCBSP_FRMSYNC_DETECT,
CSL_MCBSP_COMPAND_OFF_MSB_FIRST,
CSL_MCBSP_DATADELAY_1_BIT, //发送时，相对于同步信号延时一个clk
CSL_MCBSP_RJUSTDXENA_DXENA_OFF,
CSL_MCBSP_INTMODE_ON_READY,
//CSL_MCBSP_INTMODE_ON_FSYNC,
CSL_MCBSP_32BIT_REVERS_ENABLE
};
CSL_McbspClkSetup mcbspClock = {
CSL_MCBSP_FSCLKMODE_INTERNAL,
//CSL_MCBSP_FSCLKMODE_INTERNAL,
CSL_MCBSP_FSCLKMODE_EXTERNAL,
CSL_MCBSP_TXRXCLKMODE_INTERNAL,
//CSL_MCBSP_TXRXCLKMODE_INTERNAL,
CSL_MCBSP_TXRXCLKMODE_EXTERNAL,
CSL_MCBSP_FSPOL_ACTIVE_HIGH,
CSL_MCBSP_FSPOL_ACTIVE_HIGH,
CSL_MCBSP_CLKPOL_TX_RISING_EDGE,
//CSL_MCBSP_CLKPOL_RX_FALLING_EDGE,
CSL_MCBSP_CLKPOL_RX_RISING_EDGE,
0,
0x8,
0x5,
CSL_MCBSP_SRGCLK_CLKCPU,
CSL_MCBSP_CLKPOL_TX_RISING_EDGE ,
CSL_MCBSP_TXFSMODE_DXRCOPY,
// CSL_MCBSP_TXFSMODE_SRG,
CSL_MCBSP_CLKGSYNCMODE_OFF
};
CSL_McbspMulChSetup mcbspMul = {
CSL_MCBSP_PARTMODE_2PARTITION,
CSL_MCBSP_PARTMODE_2PARTITION,
(Uint16)0,
(Uint16)0,
CSL_MCBSP_PABLK_0,
CSL_MCBSP_PBBLK_1,
CSL_MCBSP_PABLK_0,
CSL_MCBSP_PBBLK_1
};
CSL_McbspHwSetup myHwSetup = {
&mcbspGbl,
&mcbspRxData,
&mcbspTxData,
&mcbspClock,
&mcbspMul,
CSL_MCBSP_EMU_FREERUN,
NULL
};
CSL_IntcContext intcContext;
CSL_IntcEventHandlerRecord EventHandler[100];
CSL_IntcObj intcObjEdma;
CSL_IntcHandle hIntcEdma;
CSL_IntcGlobalEnableState state;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwSetup hwSetup = {&dmahwSetup[0],NULL};
CSL_Edma3Handle hModule;
CSL_Edma3ParamSetup gParamSetupRcvPing ={ // PaRAM Set Structure for receive pingbuffer
CSL_EDMA3_OPT_MAKE // option - OPT
(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
15, CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR),
(Uint32)0x028c0000, // srcAddr- SRC
CSL_EDMA3_CNT_MAKE(2,BUFFSIZE), // aCntbCnt - (ACNT, BCNT)
(Uint32)&gBufferRcvPing, // dstAddr- DST
CSL_EDMA3_BIDX_MAKE(0,2), // srcDstBidx - (SRCBIDX, DSTBIDX)
CSL_EDMA3_LINKBCNTRLD_MAKE(0x4800, 1), //linkBcntrld - (LINK, BCNTRLD)
CSL_EDMA3_CIDX_MAKE(0,0), //srcDstCidx - (SRCCIDX, DSTCIDX)
1 // cCnt- CCNT
};
CSL_Edma3ParamSetup gParamSetupRcvPong ={ // PaRAM Set Structure for receive pongbuffer
CSL_EDMA3_OPT_MAKE // option- OPT
(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
15, CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR),
(Uint32)0x028c0000, // srcAddr- SRC
CSL_EDMA3_CNT_MAKE(2,BUFFSIZE), // aCntbCnt - (ACNT, BCNT)
(Uint32)&gBufferRcvPong, // dstAddr- DST
CSL_EDMA3_BIDX_MAKE(0,2), // srcDstBidx - (SRCBIDX, DSTBIDX)
CSL_EDMA3_LINKBCNTRLD_MAKE(0x4820, 1), //linkBcntrld - (LINK, BCNTRLD)
CSL_EDMA3_CIDX_MAKE(0,0), // srcDstCidx - (SRCCIDX, DSTCIDX)
1 // cCnt- CCNT
};
void edmaInit()
{
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamBasic1;
CSL_Edma3ChannelObj chObjXmt, chObjRcv;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannelXmt, hChannelRcv;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttrXmt, chAttrRcv;
CSL_Status status;
Uint32 i;
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
CSL_intcInit(&intcContext);
CSL_intcGlobalNmiEnable();
CSL_intcGlobalEnable(&state);
vectId = CSL_INTC_VECTID_4;
hIntcEdma = CSL_intcOpen (&intcObjEdma,CSL_INTC_EVENTID_EDMA3CC_INT1, \
&vectId , NULL);
status = CSL_edma3Init(&context);
if(status != CSL_SOK) {
printf ("Edma module initializationfailed\n");
return;
}
hModule =CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
regionAccess.region = CSL_EDMA3_REGION_1 ;
regionAccess.drae = 0xFFFFFFFF;
regionAccess.draeh = 0xFFFFFFFF ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE,®ionAccess);
dmahwSetup[12].paramNum = 12;
dmahwSetup[12].que= CSL_EDMA3_QUE_1;
dmahwSetup[13].paramNum = 13;
dmahwSetup[13].que= CSL_EDMA3_QUE_1;
CSL_edma3HwSetup(hModule,&hwSetup);
chAttrRcv.regionNum = CSL_EDMA3_REGION_1;
chAttrRcv.chaNum = CSL_EDMA3_CHA_REVT0;
hChannelRcv = CSL_edma3ChannelOpen(&chObjRcv, CSL_EDMA3,&chAttrRcv,&status);
hParamBasic1 =CSL_edma3GetParamHandle(hChannelRcv,65,NULL);
status =CSL_edma3ParamSetup(hParamBasic1,&gParamSetupRcvPing);
hParamBasic1 =CSL_edma3GetParamHandle(hChannelRcv,64,NULL);
CSL_edma3ParamSetup(hParamBasic1,&gParamSetupRcvPong);
hParamBasic1 =CSL_edma3GetParamHandle(hChannelRcv,13,NULL);
CSL_edma3ParamSetup(hParamBasic1,&gParamSetupRcvPing);
CSL_edma3HwChannelSetupParam(hChannelRcv, 13);
CSL_edma3HwChannelSetupQue(hChannelRcv,CSL_EDMA3_QUE_1);
EventRecord.handler = &eventEdmaHandler;
EventRecord.arg = (void*)(hModule);
CSL_intcPlugEventHandler(hIntcEdma,&EventRecord);
CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);
EdmaEventHook(15, tcc1Fxn);
// EdmaEventHook(1,tcc1Fxn);
regionIntr.region = CSL_EDMA3_REGION_1 ;
regionIntr.intr = 0x0000C000;
regionIntr.intrh = 0x00000000;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,®ionIntr);
CSL_edma3HwChannelControl(hChannelRcv,CSL_EDMA3_CMD_CHANNEL_CLEAR,NULL);
CSL_edma3HwChannelControl(hChannelRcv,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
/
// *((Uint32*)0x1800088) = 0x00000100;
while(1)
{
//while (!intFlag);
if (intFlag)
{
intFlag = 0;
printf ("*******completion***********\n");
}
}
}
void main()
{
Bool mcbsp1En;
memset((void*)gBufferXmtPing,0,sizeof(gBufferXmtPing));
memset((void*)gBufferXmtPong,0,sizeof(gBufferXmtPong));
memset((void*)gBufferRcvPing,0,sizeof(gBufferRcvPing));
memset((void*)gBufferRcvPong,0,sizeof(gBufferRcvPong));
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK,DEV_PERLOCK_LOCKVAL,
UNLOCK);
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0,DEV_PERCFG0_MCBSP0CTL,
ENABLE);
do {
mcbsp1En = (Bool)CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_MCBSP0STAT);
}while (mcbsp1En != TRUE);
printf("Powersaver for MCBSP 1 is enabled\n");
init_McBSP0();
edmaInit();
}
void tcc1Fxn(void)
{
intFlag = 1;
}
void init_McBSP0(void)
{
CSL_Status status = CSL_SOK;
CSL_McbspContext pContext;
CSL_McbspObj mcbspObj;
//Uint16 loopIndex;
CSL_BitMask16 ctrlMask;
//CSL_BitMask16 response;
CSL_McbspHwSetup readHwSetup;
//Uint16 maxTimeout = 1000;
//Uint16 timeout =0;
//Uint16 errCount = 0;
CSL_McbspGlobalSetup globalSetup;
CSL_McbspDataSetup rxDataSetup;
CSL_McbspDataSetup txDataSetup;
CSL_McbspClkSetup clkSetup;
memset (&readHwSetup, 0, sizeof(CSL_McbspHwSetup));
memset (&mcbspObj, 0, sizeof(CSL_McbspObj));
readHwSetup.global = &globalSetup;
readHwSetup.rxdataset = &rxDataSetup;
readHwSetup.txdataset = &txDataSetup;
readHwSetup.clkset = &clkSetup;
printf("\n***singleChannelTransmission***\n");
status = CSL_mcbspInit(&pContext);
if(status != CSL_SOK) {
printf("Mcbsp initialization failed\n");
return;
}
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL,&status);
if((hMcbsp == NULL) || (status != CSL_SOK)) {
printf ("MCBSP: Opening instance... Failed.\n");
printf ("\tReason: Error opening the instance. \
[status = 0x%x, hMcbsp = 0x%x]\n", status, hMcbsp);
exit(1);
}
ctrlMask = CSL_MCBSP_CTRL_RX_DISABLE
| CSL_MCBSP_CTRL_TX_DISABLE
| CSL_MCBSP_CTRL_FSYNC_DISABLE
| CSL_MCBSP_CTRL_SRG_DISABLE;
CSL_mcbspHwControl (hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL,&ctrlMask);
status= CSL_mcbspHwSetup (hMcbsp , &myHwSetup);
if(status != CSL_SOK){
printf ("MCBSP: Hardware setup... Failed.\n");
exit(1);
}
status = CSL_mcbspGetHwSetup (hMcbsp ,&readHwSetup);
if(status != CSL_SOK){
printf ("MCBSP: Get Hardware setup... Failed.\n");
exit(1);
}
status = hwSetupVerify (&myHwSetup,&readHwSetup);
if(status != CSL_SOK){
printf ("MCBSP: Hardware setup and Read Hardware setup parameter");
printf ("comparision ... Failed.\n");
exit(1);
}
ctrlMask = CSL_MCBSP_CTRL_SRG_ENABLE |CSL_MCBSP_CTRL_FSYNC_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL,&ctrlMask);
WAIT_FOR_2_CLK;
// ctrlMask =CSL_MCBSP_CTRL_TX_ENABLE | CSL_MCBSP_CTRL_RX_ENABLE;
ctrlMask = CSL_MCBSP_CTRL_RX_ENABLE;
CSL_mcbspHwControl(hMcbsp, CSL_MCBSP_CMD_RESET_CONTROL,&ctrlMask);
WAIT_FOR_2_CLK;
}
CSL_Status hwSetupVerify (
CSL_McbspHwSetup *hwSetup,
CSL_McbspHwSetup *hwSetupRead
)
{
CSL_Status status = CSL_SOK;
if(hwSetupRead->global != NULL) {
if(!((hwSetup->global->dlbMode ==hwSetupRead->global->dlbMode)
&&(hwSetup->global->clkStopMode == \
hwSetupRead->global->clkStopMode)
&&(hwSetup->global->ioEnableMode== \
hwSetupRead->global->ioEnableMode))) {
status = CSL_ESYS_FAIL;
}
}
if(hwSetupRead->rxdataset != NULL) {
if (!((hwSetup->rxdataset->numPhases == \
hwSetupRead->rxdataset->numPhases)
&&(hwSetup->rxdataset->wordLength1 == \
hwSetupRead->rxdataset->wordLength1)
&&(hwSetup->rxdataset->wordLength2 == \
hwSetupRead->rxdataset->wordLength2)
&&(hwSetup->rxdataset->frmLength1 == \
hwSetupRead->rxdataset->frmLength1)
&&(hwSetup->rxdataset->frmSyncIgn == \
hwSetupRead->rxdataset->frmSyncIgn)
&&(hwSetup->rxdataset->compand == \
hwSetupRead->rxdataset->compand)
&& (hwSetup->rxdataset->dataDelay == \
hwSetupRead->rxdataset->dataDelay)
&&(hwSetup->rxdataset->rjust_dxenable == \
hwSetupRead->rxdataset->rjust_dxenable)
&&(hwSetup->rxdataset->intEvent == \
hwSetupRead->rxdataset->intEvent)
&&(hwSetup->rxdataset->wordReverse == \
hwSetupRead->rxdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
if(hwSetupRead->txdataset != NULL) {
if (!((hwSetup->txdataset->numPhases == \
hwSetupRead->txdataset->numPhases)
&&(hwSetup->txdataset->wordLength1 == \
hwSetupRead->txdataset->wordLength1)
&&(hwSetup->txdataset->wordLength2 == \
hwSetupRead->txdataset->wordLength2)
&&(hwSetup->txdataset->frmLength1 == \
hwSetupRead->txdataset->frmLength1)
&&(hwSetup->txdataset->frmSyncIgn == \
hwSetupRead->txdataset->frmSyncIgn)
&&(hwSetup->txdataset->compand == \
hwSetupRead->txdataset->compand)
&&(hwSetup->txdataset->dataDelay == \
hwSetupRead->txdataset->dataDelay)
&&(hwSetup->txdataset->rjust_dxenable == \
hwSetupRead->txdataset->rjust_dxenable)
&&(hwSetup->txdataset->intEvent == \
hwSetupRead->txdataset->intEvent)
&&(hwSetup->txdataset->wordReverse == \
hwSetupRead->txdataset->wordReverse))) {
status = CSL_ESYS_FAIL;
}
}
if(hwSetupRead->clkset != NULL) {
if (!((hwSetup->clkset->frmSyncRxMode == \
hwSetupRead->clkset->frmSyncRxMode)
&&(hwSetup->clkset->frmSyncTxMode == \
hwSetupRead->clkset->frmSyncTxMode)
&&(hwSetup->clkset->frmSyncRxPolarity == \
hwSetupRead->clkset->frmSyncRxPolarity)
&&(hwSetup->clkset->frmSyncTxPolarity == \
hwSetupRead->clkset->frmSyncTxPolarity)
&&(hwSetup->clkset->clkRxMode == \
hwSetupRead->clkset->clkRxMode)
&&(hwSetup->clkset->clkTxMode == \
hwSetupRead->clkset->clkTxMode)
&&(hwSetup->clkset->clkRxPolarity == \
hwSetupRead->clkset->clkRxPolarity)
&&(hwSetup->clkset->clkTxPolarity == \
hwSetupRead->clkset->clkTxPolarity)
&&(hwSetup->clkset->srgFrmPulseWidth == \
hwSetupRead->clkset->srgFrmPulseWidth)
&&(hwSetup->clkset->srgFrmPeriod == \
hwSetupRead->clkset->srgFrmPeriod)
&&(hwSetup->clkset->srgClkDivide == \
hwSetupRead->clkset->srgClkDivide)
&&(hwSetup->clkset->srgClkSync == \
hwSetupRead->clkset->srgClkSync)
&&(hwSetup->clkset->srgInputClkMode == \
hwSetupRead->clkset->srgInputClkMode)
&&(hwSetup->clkset->srgClkPolarity == \
hwSetupRead->clkset->srgClkPolarity)
&&(hwSetup->clkset->srgTxFrmSyncMode == \
hwSetupRead->clkset->srgTxFrmSyncMode))) {
status = CSL_ESYS_FAIL;
}
}
if(!((hwSetup->emumode == hwSetupRead->emumode )&&
(hwSetup->extendSetup == hwSetupRead->extendSetup))){
status = CSL_ESYS_FAIL;
}
return status;
}
第二个文件内容
#include
#include
#pragmaDATA_SECTION(TccHandlerTable,".testMem");
EdmaTccHandler TccHandlerTable[64];
void eventEdmaHandler (
void *handle
)
{
CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle;
CSL_BitMask32 maskVal;
CSL_Edma3CmdIntr regionIntr;
Uint32 tcc;
Uint32 intr;
Uint32 intrh;
// Uint32 * a;
// Uint32 * b;
//a = (Uint32 *)0x02A01008;
// b = (Uint32 *)0x02A01068;
regionIntr.region = CSL_EDMA3_REGION_1;
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
while (regionIntr.intr || regionIntr.intrh) {
intr =regionIntr.intr;
intrh = regionIntr.intrh;
tcc = 0;
while (intr) {
maskVal = 1 << tcc;
if (intr & maskVal) {
InvokeHandle(tcc);
intr&= ~maskVal;
}
tcc++;
}
tcc = 0;
while (intrh) {
maskVal = 1 << tcc;
if (intrh & maskVal) {
InvokeHandle((tcc+32));
intrh&= ~maskVal;
}
tcc++;
}
//intFlag = 0;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,®ionIntr);
/
void EdmaEventHook (
Uint16 tcc,
EdmaTccHandler fxn
)
{
TccHandlerTable[tcc] = (fxn);
}
Bool Verify_Transfer (
Uint16 aCnt,
Uint16 bCnt,
Uint16 cCnt,
Uint16 srcBIdx,
Uint16 dstBIdx,
Uint16 srcCIdx,
Uint16 dstCIdx,
Uint8 *srcBuff,
Uint8 *dstBuff,
Bool abSync
)
{
Uint32 loopIndex1;
Uint32 loopIndex2;
Uint32 loopIndex3;
Uint8 *srcArrayPtr = srcBuff;
//unsigned int *srcArrayPtr = srcBuff;
Uint8 *dstArrayPtr = dstBuff;
Uint8 *srcFramePtr = srcBuff;
// unsignedint *srcFramePtr = srcBuff;
Uint8 *dstFramePtr = dstBuff;
for(loopIndex1 = 0; loopIndex1 < cCnt; loopIndex1++)
{
for (loopIndex2 = 0; loopIndex2 < bCnt; loopIndex2++)
{
for (loopIndex3 = 0; loopIndex3 < aCnt; loopIndex3++)
if (srcArrayPtr[loopIndex3] != dstArrayPtr[loopIndex3])
return FALSE;
srcArrayPtr = srcArrayPtr + srcBIdx;
dstArrayPtr = dstArrayPtr + dstBIdx;
}
if (abSync) {
srcFramePtr = srcFramePtr + srcCIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstFramePtr + dstCIdx;
dstArrayPtr = dstFramePtr;
}
else {
srcFramePtr = srcArrayPtr + srcCIdx - srcBIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstArrayPtr + dstCIdx - dstBIdx;
dstArrayPtr =dstFramePtr;
}
}
return TRUE;
}
Verilog程序，en产生一个上升沿就会产生一次数据，reset高电平复位，程序初始化时要有个复位信号。Temp信号没有什么用处，用于测试，clk_out是mcbsp的时钟，sync为frame信号，data为数据信号。
module REV_McBSP(clk,en,reset,clk_out,sync,data,temp);// 用于产生测试McBSP接收信号
input clk,en,reset;
output clk_out,sync,data;
output[7:0] temp;
assign clk_out = clk;
reg[7:0] counter,counter1,temp;
reg sync,data;
reg en_flag;
reg over_flag;
reg[79:0] data_send;
always @(posedge clk)
begin
if (reset)
begin
counter <= 0;
data <= 0;
data_send <= 80'h030255ae57aa65805501;
counter1 <= 0;
over_flag <= 1;
end
else
begin
if (en_flag)
begin
over_flag <= 0;
end
if (counter < 1 && counter1 < 10 &&!over_flag)
begin
sync <=1;
counter <= counter + 1;
end
else if (counter < 8 && counter1 < 10 &&!over_flag)
begin
sync <= 0;
temp = counter1*8 + counter - 1;
data <= data_send[temp];
counter <= counter + 1;
end
else if (counter >= 8 && counter1 < 10 &&!over_flag)
begin
temp = counter1*8 + counter - 1;
data <= data_send[temp];
counter <= 0;
counter1 <= counter1 + 1;
//data <= 0;
end
else if (counter1 >= 10 && !over_flag)
begin
counter1 <= 0;
over_flag <= 1;
end
end
end
reg start_flag;
reg[2:0] count2;
always @(posedge clk) //当wr_en产生一个上升沿时，产生一个持续时间为3个sck时钟周期的高脉冲。
begin
if(reset)
begin
start_flag <= 1;
count2 <= 3'd0;
en_flag <= 0;
end
else
begin
if (en)
begin
if (start_flag)
begin
if (count2 <= 2)
begin
en_flag <= 1;
count2 <= count2 + 3'd1;
end
else
begin
count2 <= 3'd0;
en_flag <= 0;
start_flag <= 0;
end
end
end
else
begin
start_flag <= 1;
en_flag <= 0;
end
end
end
endmodule
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