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u8 SPI_RW(u8 byte)
{
}
u8 SPI_RW_Reg(u8 reg, u8 value)
{
u8 status;
status = SPI_RW(reg); // Ñ¡Ôñ¼Ä´æÆ÷£¬Í¬Ê±·µ»Ø״̬×Ö
SPI_RW(value); // È»ºóдÊý¾Ýµ½¸Ã¼Ä´æÆ÷
CSN = 1; // CSNÀ¸ß£¬½áÊøÊý¾Ý´«Êä
return(status); // ·µ»Ø״̬¼Ä´æÆ÷
}
u8 SPI_Read(u8 reg)
{
u8 reg_val;
CSN = 0; // CSNÖõͣ¬¿ªÊ¼´«ÊäÊý¾Ý
SPI_RW(reg); // Ñ¡Ôñ¼Ä´æÆ÷
reg_val = SPI_RW(0); // È»ºó´Ó¸Ã¼Ä´æÆ÷¶ÁÊý¾Ý
CSN = 1; // CSNÀ¸ß£¬½áÊøÊý¾Ý´«Êä
return(reg_val); // ·µ»Ø¼Ä´æÆ÷Êý¾Ý
}
u8 SPI_Read_Buf(u8 reg, u8 *pBuf, u8 bytes)
{
u8 status, i;
CSN = 0; // CSNÖõͣ¬¿ªÊ¼´«ÊäÊý¾Ý
status = SPI_RW(reg); // Ñ¡Ôñ¼Ä´æÆ÷£¬Í¬Ê±·µ»Ø״̬×Ö
for(i=0; i
CSN = 1; // CSNÀ¸ß£¬½áÊøÊý¾Ý´«Êä
return(status); // ·µ»Ø״̬¼Ä´æÆ÷
}
u8 SPI_Write_Buf(u8 reg, u8 *pBuf, u8 bytes)
{
u8 status, i;
CSN = 0; // CSNÖõͣ¬¿ªÊ¼´«ÊäÊý¾Ý
status = SPI_RW(reg); // Ñ¡Ôñ¼Ä´æÆ÷£¬Í¬Ê±·µ»Ø״̬×Ö
delay_us(10);
for(i=0; i
SPI_RW(*pBuf++); // Öð¸ö×Ö½ÚдÈënRF24L01
CSN = 1; // CSNÀ¸ß£¬½áÊøÊý¾Ý´«Êä
return(status); // ·µ»Ø״̬¼Ä´æÆ÷
}
void SetRX_Mode(void)
{
//CE=0; //¿ÉÒÔ²»½øÐÐÀµÍ²Ù×÷£¬¿¼ÂÇ´ËʱµÄЧÂÊ
//SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // IRQÊÕ·¢Íê³ÉÖжÏÏìÓ¦£¬16λCRC £¬Ö÷½ÓÊÕ
delay_us(1500); // ÐèÒªÒ»¶¨µÄÑÓʱ£¬¾ßÌåʱ¼äµÈ´ýÑéÖ¤£¨ÊÖ²áÉÏдµÄÊÇ130us£©
}
// ½ÓÊÜÊý¾Ýº¯Êý
u8 RxPacket(u8* rx_buf)
{
sta = SPI_Read(STATUS); // ¶Áȡ״̬¼Ä´æÆäÀ´ÅжÏÊý¾Ý½ÓÊÕ×´¿ö
if(RX_DR) // ÅжÏÊÇ·ñ½ÓÊÕµ½Êý¾Ý
{
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH); // read receive payload from RX_FIFO buffer
revale =1; // ¶ÁÈ¡Êý¾ÝÍê³É±êÖ¾
}
SPI_RW_Reg(WRITE_REG+STATUS,sta); // ½ÓÊÕµ½Êý¾ÝºóRX_DRÖøߣ¬Ð´1ÇåÖжϱêÖ¾£¬Í¬Ê±Çå³ýRX FIFOS?
return revale; // ÊÇ·ñ½ÓÊܵ½Êý¾ÝµÄ±ê־λ
}
// ·¢ËÍÊý¾Ýº¯Êý
void TxPacket(u8* tx_buf)
{
CE=0; //StandBy Iģʽ
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // ×°ÔؽÓÊն˵ØÖ·
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // ×°ÔØÊý¾Ý
//SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQÊÕ·¢Íê³ÉÖжÏÏìÓ¦£¬16λCRC£¬Ö÷·¢ËÍ
CE=1; //ÖøßCE£¬¼¤·¢Êý¾Ý·¢ËÍ
delay_us(1000); //ÑÓʱʱ¼ä´ý×îСȷ¶¨£¬ÊÇ·ñÊÇ130us£¿
}
// ³õʼ»¯TX or RX Mode
void init_nRF(void)
{
delay_us(1000);
CE=0; // chip enable
CSN=1; // Spi disable
SCK=0; // Spi clock line init high
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // д±¾µØµØÖ·
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); // д½ÓÊն˵ØÖ·
SPI_RW_Reg(WRITE_REG + EN_AA, 0x00); // ƵµÀ0×Ô¶¯ ACKÓ¦´ðÔÊÐí
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // ÔÊÐí½ÓÊÕµØÖ·Ö»ÓÐƵµÀ0£¬Èç¹ûÐèÒª¶àƵµÀ¿ÉÒԲο¼Page21
SPI_RW_Reg(WRITE_REG + RF_CH, 0); // ÉèÖÃÐŵÀ¹¤×÷Ϊ2.4GHZ£¬ÊÕ·¢±ØÐëÒ»ÖÂ
//SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0X00); // disable the retr (TX mode)
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); // ÉèÖýÓÊÕÊý¾Ý³¤¶È£¬±¾´ÎÉèÖÃΪ32×Ö½Ú
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // ÉèÖ÷¢ÉäËÙÂÊΪ1MHZ£¬·¢É书ÂÊΪ×î´óÖµ0dB
SPI_RW_Reg(WRITE_REG + CONFIG, 0X0F); // 0x0f for RX (0x0e for TX mode)
delay_ms(1);
}
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SPI_RW_Reg(WRITE_REG + EN_AA, 0X00); //È¡ÏûͨµÀ0×Ô¶¯Ó¦´ð
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0X00); //ÎÞ½ÓÊÕͨµÀ
SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0X00); //È¡Ïû×Ô¶¯ÖØ·¢¹¦ÄÜ
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SPI_RW_Reg(WRITE_REG + EN_AA, 0X00); //È¡ÏûͨµÀ0×Ô¶¯Ó¦´ð
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0X01); //ʹÄܽÓÊÕͨµÀ0